PHASE 03PROTON FORGE
Prototype

Agentic engineering with deterministic acceptance gates.

Forge is a research platform for reducing iteration time across specifications, hardware, verification, firmware, and kernels—without trusting generated artifacts by default.

PUBLIC STATUS BOUNDARY

Research platform; human engineering judgment remains responsible

CODE-NATIVE SYSTEM VIEW
EDITABLE / RESPONSIVE
01Requirements
02Structured specification
03Workload model
04Design or code generation
05Compile and lint
06Golden-reference comparison
07Randomized testing
08Coverage and synthesis regression
09Human review
ACCEPTANCE RULEIndependent checks outrank model confidence.
01AGENT ROLES

Specialized assistance across one engineering trace.

Candidate roles cover specification analysis, workload characterization, design-space exploration, RTL and DV scaffolding, firmware, kernels, documentation, and regression triage.

02EVIDENCE-GATED WORKFLOW

Model confidence is never the acceptance criterion.

Artifacts move through deterministic compilation, lint, reference comparison, randomized tests, assertions, coverage, synthesis or performance regression, and review.

03RTL + DV ASSISTANCE

Generate scaffolding, tests, and reviewable changes—not unquestioned hardware.

Assistance may produce microarchitecture scaffolds, test plans, cocotb tests, assertions, and triage summaries. Independent tools must verify every accepted result.

04KERNEL GENERATION

Target constraints and differential tests surround generation.

A declarative kernel specification can lead to RVV or matrix-targeted code, but compilation, randomized shapes, edge cases, tolerance checks, and profiling decide whether it advances.

05REPRODUCIBILITY

Accepted output becomes a versioned artifact with evidence.

Inputs, tool versions, generated changes, deterministic checks, failures, and review decisions are intended to remain traceable.

06HUMAN SIGN-OFF

Architecture and acceptance remain engineering responsibilities.

Agents may accelerate analysis and implementation, but human engineers own requirements, architecture, exceptions, and final sign-off.

07CURRENT LIMITATIONS

The system is a prototype direction, not autonomous hardware development.

No claim is made that generated RTL, firmware, tests, or kernels are correct without independent verification.

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